The recent development of a microprocessor which is fabricated in the form of a MOS monolithic integrated circuit, has brought feasible and broad new range of many applications, including digital control functions such as numeric control, automotive control, elevator control, highway and rail traffic control and process control, and countless other applications within the fields of household appliances, transportation, medical electronics, test systems, and many others.
In the microprocessor system, a central processing unit (CPU) performs a master controller function since it executes stored program instructions and transmits and receives data and control signals required to perform over-all functions of the microprocessor system. The CPU sequentially executes instructions. In many applications, it is necessary to execute sets of instructions in response to request signals from various peripheral units. These requests are often asynchronous to the execution of the main program. Interrupts provide a way to temporarily suspend normal program execution so that the CPU can be freed to service these requests. After an interrupt has been serviced, the main program resumes as if there had been no interruption.
The instructions executed in response to an interrupt are called the interrupt service routine. These routines are much like subroutines except that they are called through the automatic hardware interrupt mechanism rather than by a subroutine call instruction, and all CPU registers are saved on the stack rather than just saving the program counter. An interrupt (provided it is enabled) causes normal program flow to be suspended as soon as the currently executing instruction finishes. The CPU then pushes the contents of all CPU registers onto the stack so that the CPU context can be restored after the interrupt is finished. After stacking the CPU registers, the CPU determines which request source has the highest priority if multiple interrupt requests occur, and then the vector for the highest priority pending interrupt source is loaded into the program counter. Other pending interrupt sources being not the highest are ignored. The CPU responds to the highest priority request source being executed to clear the highest interrupt request, and execution continues with the first instruction of the interrupt service routine. An interrupt is concluded with a return from interrupt (RTI) instruction, which causes all CPU registers and the return address to be recovered from the stack so that the interrupted program can resume as if there had been no interruption. If any interrupt request still exists, the CPU recognizes it and executes an interrupt again.
Interrupts can be enabled or disabled by an I-bit in the condition code register (CCR) and by local enable mask bits in the on-chip peripheral control registers. The I-bit in the CCR acts as a primary enable control for all maskable interrupts. When the I-bit is set, interrupts can become pending but will not be honored. When the I-bit is clear, interrupts are enabled to interrupt normal program flow when an interrupt source requests service.
An interrupt can be recognized at any time by the CPU, provided it is enabled. Once any interrupt source is recognized, the CPU will respond at the completion of the currently executing instruction. When the CPU decides to service an interrupt, the contents of CPU registers are pushed (stored) on the stack memory. The interrupt sequence then proceeds to the priority resolution step. After the contents of the registers have been stacked, the CPU evaluates all pending interrupt requests to determine which source has the highest priority. The interrupt sources usually have a fixed hardware-priority interrupt relationship.
When an interrupt has been serviced as needed, the CPU returns to the program that was running at the time of the interruption. During servicing of the interrupt, some or all of the CPU registers will have changed. To continue the former program as if it had not been interrupted, the registers must be restored to the values present at the time the former program was interrupted.
In order to ascertain whether such complex interrupt service is properly performed, it is necessary to carry out two performance tests defined below:
(1) Peripheral test: a test for confirming whether peripheral units provide the proper interrupt request signals; and
(2) CPU test: a test for confirming whether the CPU properly executes an interrupt operation when receiving interrupt request signal(s).
However, there are several problems in carrying out both performance tests. Because the peripherals and the CPU are directly connected through interrupt request lines, whenever the Peripheral test should be done, the CPU necessarily executes the interrupt service. In other words, the Peripheral test can not be done without the actual interrupt execution, and therefore much time and troublesome procedure are required.
In the CPU test, there is a need to cause all peripheral units to actually provide their interrupt request signals concurrently, sequentially and in other ways. Accordingly, the CPU test requires a very complex test procedure and much amount of time, and further requires a variety of complex test programs for each microprocessor chip having different sets of peripherals.